Asic Verification Engineer Resume
Objective : As an ASIC Verification Engineer, trained with chip-level requirements validation and characterization including functional and parametric collections.
Skills : Proficiency in Hardware Description Languages.
Description :
- Planned and worked on the strategic direction of the methodology for the testbench with advanced methodology.
- Exposured to Computer Architecture, ASIC design and verification methodology are required
- Exposured to simulation tools like VCS, IES, and debug tools like Debussy, and GDB.
- Understood memory subsystem micro-architecture, cache topologies and policies, memory management, interconnects, and/or arbiter designs is a huge plus.
- Trained with Universal Verification Methodology (UVM), SystemVerilog checkers, and scoreboards. Assertion-based verification, Semiformal Verification (SFV).
- Developed test plans, tests, and verification infrastructure for verifying global IP across multiple products.
- Created detailed verification plans based on design specifications, identifying test cases, and developing verification environments.
Experience
2-5 Years
Level
Executive
Education
Bachelor’s Degree in Electrical Engineering
Senior ASIC Verification Engineer Resume
Summary : As a Senior ASIC Verification Engineer, defined the verification scope, and contributed to the development of verification infrastructure related to high-speed IO protocols and memory coherence, verified firmware code, with specific attention on verifying hardware/firmware interactions.
Skills : Experience with simulation tools, Knowledge of scripting languages.
Description :
- Collaborated with architects, designers, and software engineers across sites to accomplish goals.
- Trained with verification methodology (UVM or similar), creating reusable verification components.
- Exposured to design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi interactive, Debussy, GDB).
- Trained with embedded microcontrollers (RISCV or similar) and/or debugging firmware code.
- Learned and developed opportunities from a highly diverse and talented peer group, including in a wide range of fields, from Artificial Intelligence and Computer Vision to Systems and Device Engineering.
- Provided an exciting opportunity to design and verify digital designs on leading-edge process nodes producing game-changing complex integrated circuits (ICs) in support of mission-critical programs.
- Trained with industry-standard best practices for design, verification, testing, and deployment.
Experience
10+ Years
Level
Senior
Education
Bachelor’s Degree in Computer Science
Asic Verification Engineer Resume
Summary : As an ASIC Verification Engineer, understand object-oriented programming principles, constrained random stimulus, and a coverage-driven verification approach.
Skills : Familiarity with FPGA prototyping and analytical Skills.
Description :
- Built a testbench for a medium complexity block using System Verilog and UVM.
- Wrote random tests, directed tests, error tests and performance tests for a block of medium complexity using System Verilog and UVM.
- Developed, maintained, and supported the UVM verification environment.
- Debugged tests with design engineers to deliver functionally correct design blocks OOPS, randomization, constraints, interfaces writing and Analyzed functional coverage, and assertions.
- Generated and analyzed code coverage and writing waivers.
- Analyzed architectural trade-offs based on features, performance requirements, and system limitations.
- Utilized various EDA (Electronic Design Automation) tools and software for simulation, debugging, and analysis, such as Synopsys, Cadence, or Mentor Graphics tools.
Experience
7-10 Years
Level
Management
Education
Bachelor's In Computer Science
Asic Verification Engineer Resume
Headline : As an ASIC Verification Engineer, defined, developed, and automated flows and methodologies to efficiently build, deploy, and verify generated RTL, and built verification components using SV/UVM methodology.
Skills : Problem-solving capabilities and communication Skills.
Description :
- Drove coverage-based verification closure.
- Collaborated with design teams across NVIDIA to find corner cases and resolve verification-related issues.
- Trained in pre-silicon verification (UVM, SystemVerilog), System-On-Chip design/implementation flow, and design automation.
- Exposured to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB).
- Trained in object-oriented programming desired.
- Verified the design and implementation of the industry's leading GPUs.
- Ran simulations using hardware description languages (HDLs) such as VHDL or Verilog to verify the functionality of the ASIC design.
Experience
5-7 Years
Level
Executive
Education
Bachelor's In Computer Science
Senior Asic Verification Engineer Resume
Summary : As a Senior ASIC Verification Engineer, knowledgeable of ARM/MIPS/RISC-V Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation.
Skills : SystemVerilog, Verilog, VHDL.
Description :
- Worked on cross-disciplinary teams of highly talented and motivated engineers on projects of national importance.
- Designed and verified advanced architectures for high throughput signal processing, SoCs (Systems on Chip), radar, PNT, and secure hardware solutions.
- Deployed designs on FPGA or SDR platforms, from RTL, through simulation and synthesis, to lab bring-up and debugging.
- Developed low-size, weight, power, and cost (SWaP-C), highly integrated circuits.
- Verified algorithms in SW/HW on embedded systems.
- Led testing of custom prototypes in the lab and on automated test equipment (ATE).
- Verified the design, architecture, and micro-architecture using advanced verification methodologies.
Experience
10+ Years
Level
Senior
Education
Bachelor's In Computer Science
Asic Verification Engineer Resume
Objective : As an Asic Verification Engineer, knowledgeable of assertion-based formal verification, documented verification plans, test cases, results, and any issues encountered, as well as maintaining thorough records of the verification process.
Skills : UVM (Universal Verification Methodology), OVM (Open Verification Methodology).
Description :
- Trained with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, and I2C.
- Designed and implemented testbenches, including test cases, to simulate the ASIC design under various conditions and scenarios.
- Identified, diagnosed, and resolved design issues, bugs, and discrepancies uncovered during the verification process.
- Performed code and functional coverage analysis to ensure comprehensive verification and identifying gaps in test coverage.
- Automated verification processes using scripting languages like Python, Perl, or TCL to improve efficiency and repeatability.
- Worked closely with design engineers, system architects, and other stakeholders to understand design requirements, provide feedback, and suggest improvements.
- Evaluated the performance of the ASIC design and ensuring it meets the required specifications and standards.
Experience
2-5 Years
Level
Executive
Education
Bachelor's In Computer Science
Asic Verification Engineer Resume
Objective : As an Asic Verification Engineer, debugged issues independently, developed test benches and tests for FPGAs and ASICs, assisted in root-causing RTL bugs, and developed verification models, instrumented TB for functional and code coverage.
Skills : Synopsys VCS, Cadence Incisive.
Description :
- Tested plan and coverage analysis of the block and SOC-level verification.
- Trained with ASIC design verification, synthesis, timing/power analysis, and DFT.
- Required in ASIC Verification, including proficiency in UVM and System Verilog.
- Trained with modern SoC design architectures, ARM/MIPS type processor cores, Ethernet, Networking, and Data Communications.
- Trained in high-performance and low-power design techniques.
- Trained in FPGA and emulation platforms, Knowledgeable of SOC architecture.
- Ensured that the ASIC design complies with industry standards, protocols, and regulations.
Experience
2-5 Years
Level
Executive
Education
Bachelor's In Computer Science
Senior Asic Verification Engineer Resume
Summary : As a Senior Asic Verification Engineer, ensured the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks, trained with scripting languages and build tools (TCL, Python, CMake).
Skills : Organizational Skills and strong time management abilities.
Description :
- Trained with Verification and/or Synthesis tools from industry-leading EDA vendors such as Cadence, Synopsys, and/or Siemens.
- Developed the block-level, sub-system, and full-chip verification environment and tests to implement test plans.
- Worked closely with design and architecture teams to understand the functional and performance goals of the design.
- Worked together to make the design-under-test work under all specified circumstances.
- Triaged and debugged functional and performance issues with the design-under-test.
- Handled bug tracking and coverage convergence.
- Performed diagnostic and post-silicon validation tests in the lab.
Experience
10+ Years
Level
Senior
Education
Bachelor's In Computer Science
Asic Verification Engineer Resume
Headline : As an Asic Verification Engineer, understood the design and implementation of your unit, defined the verification scope, developed the verification infrastructure verified the correctness of the design, and collaborated with architects, designers, and pre and post-silicon verification teams to accomplish your tasks.
Skills : Mentor Graphics ModelSim/Questa, Verilog, VHDL.
Description :
- Trained in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
- Crafted test bench environments for unit and system-level verification.
- Trained with processor verification, including instruction pipelines and caches, is desirable.
- Participated in the development of UVM environments to verify RTL at block, unit, and SoC levels.
- Wrote and executed tests according to verification plans.
- Collected and analyzed coverage results.
- Conducted regression testing to ensure that changes and updates to the design do not introduce new issues or regressions.
Experience
5-7 Years
Level
Executive
Education
Bachelor's In Computer Science
Asic Verification Engineer Resume
Summary : As an Asic Verification Engineer, executed formal verification of block level RTL, participated in post-silicon verification, trained in one or more scripting languages (TCL, Python, Perl, Shell-scripting).
Skills : Python, Perl, Shell scripting, TCL.
Description :
- Trained in test bench development.
- Maintained existing DV environments and enhanced them.
- Constructed testbench including scoreboard, agents, sequencers, and monitors for new blocks.
- Wrote test plans, developed test cases, debugged regression failures, and drove to module verification closure.
- Ensured complete verification coverage through implementation and review of code and functional coverage.
- Verified complex blocks, clusters, and top-level for SoC.
- Built test benches from scratch, hands-on experience with System Verilog constraints, structures, and classes.
Experience
7-10 Years
Level
Management
Education
Bachelor's In Computer Science
