A Design Verification Engineer is hired to work alongside the design engineers in verifying and validating circuit designs. A well-drafted Design Verification Engineer Resume mentions the following core duties and responsibilities – developing design standards and guidelines and ensuring quality and performance; performing layout, design, feasibility, and electrical verification of circuit components; participating in design reviews and suggesting corrective actions; preparing design verification plan based on design specifications, and maintaining design verification environment and tracking design bugs.
To ensure success in this field, the following skills are required – advanced knowledge of production process and quality control procedures, familiarity with mechanical and electrical testing systems and tools; detailed knowledge of testing methodologies; knowledge of industrial manufacturing procedures; and excellent analytical and troubleshooting skills. A bachelor’s degree in mechanical or electrical engineering is commonplace among job applicants.
Headline : Actively seeking full time opportunities to pursue the role of Enterprise Systems/CRM Functional Consultant to leverage the experience and skills acquired through Master's Program at Georgia State University.
Packaged testing Technical lead for IEU verification.
IEU tested bench development with an emphasis on functional coverage and scoreboard checks.
IEU Tested plan development.
Provided support to Product Test Engineers by assisting with pattern debug on the ATE and correlating failures with simulation results to pinpoint any issues.
Tested patterns consisted of functional tests, boundary scan patterns, and DC Parametric tests(IO levels and tristate modes).
Played a critical role in creating test benches in Specman (new hardware verification language - HVL), including constrained random opcode generators to exercise desired code and corner cases to test instruction prefetch cache, pipelined load/store, and debug blocks.
Experience
5-7 Years
Level
Executive
Education
GED
Design Verification Engineer Resume
Summary : Design Verification Engineer Professional with over 42 years of Process, Nuclear, Fossil Fuel, Petro-Chemical, Natural Gas and Steel experience. Extensive background in Project Management, Estimating, Planning, Scheduling, Safety, Welding, Training, Start-Up and Maintenance. I have a strong working knowledge of ASME, ANSI, AWS and API Codes, along with many Site Specifications.
Skills : Software: Windows, Linux, Programming And Scripting.
Description :
Owned verification and test plans for several IP of a SOC consisting of the footprint of how to fully verify integrated IPs for the last two projects.
Completed the activity within the time frame based on a schedule.
Tested plans consisted mostly of functional C test cases, however, Specman and Formal Verification were also implemented.
Tested cases covered basic hookup, correct bus architecture to/from multiple processors (DSP and ARM), interrupts, resets, clocks, and any specific I/O's of the IP being verified.
Used toggle coverage in VCS simulations to grade port connectivity of the IP boundary to make sure 100% of the IP ports are properly integrated into the SOC.
Excluded some ports once approved.
Created and debugged test cases used to validate designs before tape-out and converted the test cases to patterns used on Automated Test Equipment (ATE).
Experience
10+ Years
Level
Senior
Education
B.S. In Electrical Engineering
Design Verification Engineer Resume
Headline : Supporting and participating in the technical activity, and also Designing, developing, analyzing, documenting, and supporting testing of products, systems or subsystems.
Skills : FPGA Firmware Design, Multitaking.
Description :
Collaborated with design and applications teams to build a real-world video test case to exercise component data transfers in a video system and characterize performance.
Demonstrated architectural changes required to utilize direct memory access (DMA) to minimize CPU control.
Verified a system-on-a-chip (SOC) test chip with two generations of ZSP cores.
Authored tests to verify execution of opcodes leveraging VCS, NCSim, Specman, and Debussy.
Led design verification for a new multi-channel AHB master using Specman.
Developed a verification plan and created a scoreboard to verify master's operation.
Highlights Served instrumentally in conducting verification of new core blocks for the second generation of the company's superscalar digital signal processor (DSP).
Experience
5-7 Years
Level
Executive
Education
MS In Electrical Engineering
Design Verification Engineer Resume
Summary : A competitively driven electronics engineer with a record of ensuring products shipped to customers is functional and free of any defects. Background and expertise include Analog and Digital systems test and Troubleshooting ISO 9000 implementation.
Skills : Designing Skills, Verification Engineer.
Description :
Enabled tracking opcode movement through the pipeline during stalling by developing a trace module in Verilog to track instructions executed each clock cycle and demonstrate the resulting register updates and memory accesses as part of the main core-level test bench.
Developed test plans and test templates for new features.
Provided technical direction to team members and help with debugging.
Worked on verification of debugging bus feature for different blocks of the chip.
Designed the driver to select different Test modes of the chip through the JTAG interface.
Wrote a test program for an automation test machine to test the power supply.
Made wire harness for the testing machine, interface with development teams, work with the vendor to solve issues; authorize, review, document test procedures, and test reports.
Experience
7-10 Years
Level
Management
Education
MS
Design Verification Engineer Resume
Summary : Reviewing customer specifications and requirements, and under direction, develop designs to best support them, including cost as a key design variable, and also Specifying and evaluating supplier components, subsystems, and services.
Skills : Programming Languages Include C/C++, Verilog, Perl, Shell Script, C#, MatLab, VHDL. Simulation Work Performed Through Synopsys DVE.
Description :
Performed Design Verification on ASIC RTL for large shared memory HPC hubs.
Wrote long term test plans, 1-2 years, for verifying sections of the chip (chipset) based on available documentation and various communications with logic designers.
Composed fully documented diagnostic suites in C++, documented via Doxygen, for carrying out the test plan with directed and random diagnostic testing.
Created model environments in C++ to predict the behavior of a chipset being tested, or to simulate another part of the chip, mimicking realistic behavior.
Overhauled existing diagnostic suites to standardize key elements across chipset environments and increase re-usability of library code (typically done through Perl scripts).
Debugged potential bugs using various output, Valgrind, and DVE wave viewer.
Created Verilog testbeds for attaching diagnostic environments to the RTL being tested.
Experience
7-10 Years
Level
Management
Education
GED
Design Verification Engineer Resume
Headline : Seeking a Design Verification Engineer position with an outstanding career opportunity that will offer a rewarding work environment along with a winning team that will fully utilize management skills.
Attended engineering Validation Builds in China for Xbox consoles and participated in debugging manufacturing initiatives to capture failures and improve test coverage.
Debugged / troubleshooting Complex PCB Systems.
Suggested improved routing and termination schemes.
Developed Engineering Test Strategies, Plans, and Procedures to analyze, test, and qualify Xbox console system and components.
Created regressions for the diagnostic suite to continually test random diagnostics plus all previously verified sections of the chipset at regular intervals.
Performed code coverage on RTL to guarantee every aspect of the chipset was being exercised.
Created a new private model, with a new feature, add-in for each rtl miles stone in order to validate them during weekly regression.
Experience
5-7 Years
Level
Executive
Education
GED
Design Verification Engineer Resume
Objective : Result oriented and dynamic engineer with wide exposure in ASIC design verification. Comprehensive knowledge of verification tools and methodologies. Looking for a position as an ASIC verification engineer in a prestigious and growing organization.
Built code and released for test on a daily basis.
Managed and maintained Servo Regression, Robustness, and Batch tests in CD/DVD storage.
Characterized Servo system in optical storage.
Monitored changes in servo firmware and implemented servo test software through Matlab automation scripts.
Documented and performed reference on hardware, firmware, software, loader, and Optical Power Unit Checked out files from Clear Case (source code control).
Modified with an editor (Codewright), also update the firmware version.
Compiled and linked code with ZDK (ZSP Development Kit) software tools.
Experience
2-5 Years
Level
Executive
Education
Bachelor Of Science
Design Verification Engineer Resume
Headline : Specializations including function verification, test bench using System-Verilog OVM/UVM, reusable flow as well as another bench environment for the subsystem and full-chip level. Developing test plans, and running tests using random variables, running, debugging test,s and collecting coverage.
Responsible for creating test bench, debugging, and ramping up test (improve the number of test pass) and run weekly regression for latest Cannon Lake (CNL A0, B0) relating to GT (graphic) and full chip (CPU).
Made sure the test covers all-new add-on features.
Developed test suite using system Verilog, OVM, stargate for concurrency, aperture: IA, OPI test according to the test plan.
Concurrency worked with RTL team, DA team to improve a number of a test pass.
Enabled, collected, and monitored coverage for all related IA, GT test.
Worked with rtl team to improving coverage based on weekly basic.
Enabled a difference OPI test flow (which defines main traffic from PCH from south bridge to main CPU), gtpm, aperture test, and concurrency test flow (using system verilog and OVM) to verify difference function for full chip flow.
Experience
5-7 Years
Level
Executive
Education
MS
Design Verification Engineer Resume
Summary : To obtain a Design Verification Engineer position at your organization where I can provide my proven knowledge and skills that allows me the opportunity to contribute to the overall success of the organization.
Designed and developed test plan, solder re-work, and repairs test board to test Xbox and Surface power supply.
Worked with schematics and debug and analysis Xbox, surface, surface hub, HoloLens power supplies.
Documented, problem-solving, and assembly.
Debugged and troubleshoot test circuit board issues.
Soldered and replaced test board and power supply components.
Used Cadence tool to design test board, board layout and send the board to fabricate.
Verified power supply issues, test power efficiency, ripple voltage, transient response, and AC inrush current with DC loader and Xbox console.
Experience
7-10 Years
Level
Management
Education
MS
Design Verification Engineer Resume
Headline : Supporting the program design to cost and design for manufacture requirements, Developing prototypes to retire key development risks as directed, and also Communicating clearly (written and oral) with other company personnel and the customer as required.
Skills : Verification System, Hardware.
Description :
Played a key role in tape out of next generation 10G Wi-Fi chip project.
Created test plan for slave sub system.
Ported System Verilog based verification environment and wrote test cases to verify slave subsystem (I2C, UART, Timers, Watchdog Timer and GPIO) of SoC.
Developed test bench and test cases for the CQE (Control queuing Engine) interface which is responsible for exchange of information across the Processors.
Responsible for automation of execution/reporting of regressions and maintaining multiple regression suites.
Wrote C code, generated hex files and integrated Hex files in system Verilog tests verifying register read/writes through real cpu.
Verified the default value and access of all register space of chip through bfm read/write.
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