DFT Engineer Resume
Objective : As a DFT Engineer, provided tool support to design team members implementing System-on-Chip (SOC) designs (Synthesis, Static Timing, DFT, Place, and Route tools). Provided technical support/expertise on Synopsys test automation tools in a wide variety of application scenarios.
Skills : Digital Circuit Design, Testing Methodologies.
Description :
- Designed and verified for Clock/JTAG/Analog/DFT IP. Scan Insertion, ATPG, scan verification, and pattern generation.
- Created and maintained DFT timing constraints. Worked with Marketing, Probe, Assembly, Test, Process Integration, CAD, Verification Engineering, and Product Engineering groups to ensure proper testing and manufacturability of products.
- Worked closely with Product Engineering to ensure that test mode definitions, and documentation include all required functionality.
- Designed, standardized, and documented test methods and modes to facilitate common test flows and coverage on all designs.
- Understood the current manufacturing test flow to provide circuit advice to the entire department.
- Ensured that new technologies include the needed test mode designs to allow for full fail coverage testing.
- Performed circuit simulations using standard industry simulators. Assisted Verification Engineering with test mode verification plans.
Experience
2-5 Years
Level
Executive
Education
B.E.E
DFT Engineer Resume
Objective : As a DFT Engineer, provided recommendations about design improvements to increase the test coverage, decrease the Total Cost Of tests, and reduced operational costs in the long term. Worked with customers and/or product designers to get the recommended changes included in future design revisions.
Skills : DFT techniques and methodologies.
Description :
- Executed Automatic Test Pattern Generation (ATPG) and conduct the pattern re-simulation and gate level simulation. Used scripting languages to automate process flow.
- Designed for Testability analysis of electronic assemblies. Used of test analysis tools, such as Siemens TestExpert, to determine the test accessibility of PCBAs.
- Trained and mentored other test engineers. Worked with extended teams to develop project schedules and execute projects to completion.
- Generated, verified, and debugged HDL and firmware-based test cases for DFT features of new Flash-based FPGA families.
- Improved, extended, and ported existing DFT circuits and concepts to all FPGA family members.
- Developed test benches and documented test plans. Supported failure analysis and helped with silicon bring-up and debugging.
- Interfaced and collaborated with cross-functional teams in all activities. Participated in chip-level DFT architecture definition.
Experience
2-5 Years
Level
Executive
Education
BSCE
DFT Engineer Resume
Summary : As a DFT Engineer, developed test plans, Incorporated the features in a test case, and Execution/Automation of the test cases. Testcased would be written in Verilog/System Verilog/VHDL. Developed white papers on methodology and other documentation as may be required for projects.
Skills : Verilog, VHDL.
Description :
- Worked closely with the back-end team on chip-level planning, timing closure, and DFT. Designed for testing and design for manufacturing.
- Developed strategy for memory testing and generating MBIST. Worked with cross-functional IP and SOC teams to define a strategy for DFT architecture, verification, and design flow automation.
- Managed the development of software, scripts, and other support technology to enable automated construction and verification of DFT logics in complex SoC design or IP Subsystems.
- Worked with senior management to define goals and develop strategies for the group.
- Contributed throughout the whole development and give early feedback to the Concept, Architecture, and Design Teams for possible issues for DFT.
- Defined, developed, and improved DFT process flows and methodologies for continuous improvement.
- Defined and develop scripts for automatic scan insertion. Generated test patterns and simulated with and without timing annotation.
Experience
7-10 Years
Level
Management
Education
B.E.E
DFT Engineer Resume
Headline : As a DFT Engineer, worked with Physical Designers to validate the DFT timing constraints. Worked with RTL Designers to verify test design rules. Worked with Test Engineers to bring up the patterns on the ATE Automated Test Equipment. Helped develop and deploy DFT methodologies for our next-generation products.
Skills : Tcl, Simulation, and verification tools.
Description :
- Debuged test failures on silicon products in support of Release to Production.
- Worked closely with IC Design during test plan and DFT definition, pre-silicon verification(chip level verification), and post-silicon validation.
- Worked closely with the IP test development team defining test schemes and implementation styles.
- Assisted with silicon debugging in the event of yield-limiting issues or returned materials.
- Worked with Product Engineer to address Yield, Design & Quality issues during the New Product Introduction phase and to address any post-production issues.
- Defined scalable pattern methodologies to efficiently test highly configurable embedded SERDES, DDR Interfaces, and DAC/ADC hardware.
- Defined DFT requirements for next-generation products to improve test coverage or time.
Experience
5-7 Years
Level
Executive
Education
BSCE
DFT Engineer Resume
Headline : As a DFT Engineer, drove the test quality of the products from Design to Production. Participated/contributed in silicon bring-up, characterization, and silicon test. Defined and implemented various DFx features.
Skills : ASIC design methodologies, Analytical.
Description :
- Defined and implemented stuck-at and at-speed techniques. Experienced running test compression flow.
- Experienced trading off test options with product performance and schedule requirements.
- Created and released full test programs for device screening.
- Resolved design and flow issues related to DFT, identify potential solutions and drive execution. Define DFT strategy and methodologies.
- Defined test structures, debug structures, and test plans. Created test vectors simulate in various modes.
- Collaborated with the physical design team to close requirements. Validated DFT requirements are being met.
- Worked with designers to increase test coverage, debug observability, and flexibility. Verified post-PD designs meet DFT requirements.
Experience
5-7 Years
Level
Junior
Education
B.E.E
DFT Engineer Resume
Headline : As a DFT Engineer, scanned flow development, ATPG pattern generation, verification, and coverage analysis. Worked with Mentor/Siemens DFT Tessent tool for scan/MBIST/scan/IJTAG insertion and verification. Worked with Cadence DFT tools Modus and Genus.
Skills : Problem-Solving, Communication.
Description :
- Experienced or familiarised with back-end chip design, Timing, and CDC flows is a plus. Posted Silicon experience in Pattern conversion for Testers, Pattern Bring-up & Debug, and Silicon Characterization.
- Worked on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification, and post-silicon validation on some of the industry's most complex semiconductor chips.
- Owned and worked with cross-functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST, and scan compression.
- Hands-on experienced with Cadence Genus, and Modus tools, Exposure to low-power techniques.
- Led most complex and cutting-edge network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture to implementation, verification, timing closure, and ATE pattern bring up.
- Built a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and helped solve key infrastructure challenges facing our customers.
- Possessed excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools.
Experience
5-7 Years
Level
Executive
Education
BSCE
DFT Engineer Resume
Summary : As a DFT Engineer, Experienced or working knowledge of SERDES, Analog /mixed-signal DFT techniques (like IOBIST, loop-backs, etc..) is a plus. Experienced in the implementation of MBIST for memories and knowledge of repair schemes, and algorithms is a must.
Skills : Interpersonal, Quality Assistant.
Description :
- Helped mentor junior engineers on test designs and trade-offs including cost and quality.
- Experienced in Silicon debugging and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.
- Drove/pushed the state-of-the-art in the areas of testability, debugging, and quality, in order to aggressively deliver low DPPMs, while optimizing the cost for testing.
- Exposured to cross-functional areas including RTL & clocks design, STA, place-n-route, and power, to ensure we are making the right trade-offs.
- Expertised with commercial test generation tools for large complex designs.
- Experienced in generating test patterns and analyzing and debugging test failures.
- Experienced with RTL simulation, synthesis, and back-end implementation flows.
Experience
7-10 Years
Level
Management
Education
B.E.E
DFT Engineer Resume
Objective : As a DFT Engineer, performed ATPG simulations and testing. Led post-silicon test and debug efforts. Developed methodologies, processes, and tools for DFT for deployment on several projects. Trained junior staff in DFT methodologies.
Skills : Planning, Technical Skills.
Description :
- Familiared with different test pattern formats such as STIL, WGL, SVF, VCD, eVCD and ATE fail catalogs.
- Experienced in ATE pattern generation/conversion, Virtual Tester simulation, and Bench CSV generation is required.
- Familiared with JTAG/APB/AHB/AXI based protocols and experience with design and debugging of functional/AMS/HSIO patterns on ATE/Bench.
- Partnered with ATE team on Silicon Debug and ensure the stability of the pattern across voltage/temperature/process corners.
- Partnered with SLT/SVE/Bench team on developing functional/AMS/HSIO test pattern to meet target DPPM.
- Explored new flows and simulation tools and ideas for continuous improvement.
- Experienced with scripting languages like Python, Perl, skill, tcl, or equivalent to automate flows is a plus.
Experience
2-5 Years
Level
Executive
Education
BSCE
DFT Engineer Resume
Headline : As a DFT Engineer, Experienced with Mentor testkompress and/or Synopsys Tetramax/DFTMAX. Understood Design For Test methodologies and DFT verification experience IEEE1500, JTAG 1149. x, scan, memory BIST, Experienced with VCS simulation tool, Perl/Shell scripting and Verilog RTL design, Patterned generation, verification, and delivery to ATE team.
Skills : Time Management, Analyst.
Description :
- Supported and worked closely with automotive customers (with special emphasis on in-system tests using LBIST & MBIST) and non-automotive customers in defining DFT requirements and specifications for the ASIC.
- Designed and Verification of DFT logic and components.
- Generated structural test vectors, analysis, and coverage improvement. Generated timing constraints for the various DFT modes.
- Worked with implementation teams on DFT STA, logical, physical, and power issues.
- Supported ATE team with test vector porting, diagnosis, and physical failure analysis.
- Experienced with Industry standard DFT/ATPG EDA tools like Tessent/TestMax/Modus. Experienced with simulators and waveform debug tools.
- Defined & documented DFT requirements/Specifications for IP/Block and Chip level.
Experience
5-7 Years
Level
Executive
Education
B.E.E
DFT Engineer Resume
Summary : As a DFT Engineer, worked with 3rd party IP vendors to integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a streaming scan fabric with a sequential scan compressor and decompressor. Worked with DFT Solutions Vendors to port those patterns at the top level, to implement Memory BIST interface in high-performance processor IP, and to implement high-speed I/O for the logic scan test.
Skills : Vendor, Scanning.
Description :
- Planned and Inserted MBIST and memory repair (BISR) at RTL. Generated and ported IJTAG ICL/PDL and STIL patterns for MBIST, ATPG, and JTAG tests.
- Worked with the Test Engineering team during Silicon bring-up and created flow/scripts necessary for debugging/diagnosing compression LPC ATPG patterns (stuck-at/at speed), and MBIST patterns on ATE for development and production programs.
- Worked with the backend team for the MBIST/Scan mode constraints generation, scan reorder, VCDs for IR drop analysis during DFT, ECO changes and formal verification (LEC), and timing closure.
- Experienced with inserting EDT, wrapper cells, and OCC. Analyzed DFT DRC violations and fault coverage analysis.
- Expertised in ATPG. Debug and resolve ATPG DRC and chain trace issues.
- Experienced in debugging tester/ATE failures, silicon bring-up, and yield and test time improvement.
- Experienced in Perl/TCL scripting and good verbal/written communication skills.
Experience
7-10 Years
Level
Management
Education
Electrical Engineering
