A Verification Engineer undertakes the duty of designing and implementing testing procedures and to determine if products work as intended. The job description entails taking responsibility for creating the initial product verification methodologies, and developing testing plans. A well-written Verification Engineer Resume includes the following duties – meeting with product designers and determining functionality protocols; reviewing the product designs, and noting points of failure; designing verification methodologies based on product designs; determining testing environments, and verification tools; planning the methods of sequence for testing operations, and conducting quality control inspections.
The most sought-after skills for the post include the following – knowledge of production process and quality control procedures; knowledge of mechanical and electrical testing systems and tools; a good understanding of testing methodology; and troubleshooting skills. A degree in mechanical or electrical engineering is commonplace among job applicants.
Objective : A result-oriented Verification Engineer experienced in all aspects of Software Development Life Cycle (SDLC). I have extensive experience in analysis of Software Requirement Specification (SRS), Functional Requirement Specifcations (FRS), software design documents (SDD), use cases design documents and development of software test plans, test strategy, test cases, and traceability matrix. I enjoy analytical work, interaction with clients and committed to delivering high quality and timely results.
Skills : SDLC, Agile Development, HP Quality Center, JIRA, STLC, Regration Test, Integration Test.
Description :
Involved in the understanding of functionality and design of different applications based on the Requirement Specification Document.
Captured Test Cases and Test Results in Quality Center and documented and prepared the release notes as part of the project deliverables.
Investigated software bugs and Interfaced with developers to resolve technical issues and reporting the bugs to all concerned.
Investigated requirements and interfaced with developers to resolve issues and reporting the issues to all concerned.
Outstanding issued are documented and managed through Quality Center.
Maintained Requirement Traceably Matrix (RTM) after developing and updating Test Cases Created, Maintained, and Executed Manual Test Scripts in Quality Center.
Analyzed and identified defects, and logged defects with detailed specification into Quality Center as they relate to Test Cases.
Experience
2-5 Years
Level
Executive
Education
Business Administration
Verification Engineer Resume
Objective : Highly skilled Verification Engineer professional with 8+ Years of experience in the ASIC Design and Verification. Verification of Various Domain modules across IP, Sub-system and SOC. Proficient in latest verification methodologies for multimillion gate ASIC verification skills. Expert in Metric/Coverage Driven Verification using System Verilog and various methodologies like UVM, OVM.
Skills : Computer Network, Verilog, Digital Design, C Programming, VCS, Modelsim, PCIE, RTL Design, Constraint Random Verification, Perl, SystemVerilog OOP Testbench, UVM.
Description :
Used 180nm technology and it has a multimillion gate count.
Responsible for Understanding the Architecture & design Specification sheet.
Responsible for Verification Plan and Test plan creation.
Responsible for verification component development for AHB slave.
Responsible for development of verification Test Bench using SV-OVM.
Analyzed test results to ensure existing functionality and recommends corrective action.
Worked with Users and Business Analysts to define and design test scenarios and test data.
Experience
2-5 Years
Level
Executive
Education
Bachelor Of Technology
Verification Engineer Resume
Objective : Responsible for Writing coverage monitors, checkers, assertions and collect statistics, and also Creating tools, scripts and utilities to aid in creating stimulus and analyzing the results of simulations, including performance measurements.
Skills : Embedded C, C++ ,Matlab , NI LabView ,NI TestStand, AQTime, Linux Shell scripting, Adobe Dreamweaver, Windows, Linux. Protocols: USB, Modbus, Proxibus, SensorMAC.
Description :
Responsible for random instruction generation using a third party tool Responsible for the Integration of different PowerPC releases with the L2 cache and memory system.
Built and ran regressions to verify the platform environment and releases to the whole group for full regressions.
Responsible for running L2 with PowerPC in Emulator.
Developed the detail Test plan and created assembly level tests to run in emulator.
Developed a verification environment in SystemVerilog (UVM) for a memory controller and a streaming cache (between ARM L2 cache and the memory).
Verified several filters and the memory access arbiter.
Used of the suite of Cadence.
Experience
2-5 Years
Level
Junior
Education
B. TECH In Electronics
Verification Engineaer Resume
Summary : Development of constrained random verification infrastructure I n System Verilog using UVM/OVM Ability to conceptualize and implement test plans, debugging RTL and verification assertions in regressions to improve and maintain design quality Understanding of OOPs concepts and ability to implement them in design verification components.
Skills : MS Office, Aiding SKills, Analyzing Skills.
Description :
Supported mechanical verification by composing protocols, test cases, and reports.
Assisted with electrical and firmware verification activities.
Maintained document control.
Maintained configuration control of prototypes.
Aided in writing global and site-wide procedures.
Aided in Design Failure Mode Effect and Analysis (DFMEA).
Maintained Design History Files and Index.
Experience
7-10 Years
Level
Management
Education
BS
Verification Engineer Resume
Objective : Dedicated, results-oriented Verification Engineer, with experience in embedded software design, development, testing, System administration & Network administration. Efficiently operated multiple projects across geographic locations. Creative problem solving and time management skills coupled with outstanding interpersonal skills facilitate tangible and seen results.
Tested cases and integrated Test Procedures are developed from system requirements.
Tested scripts are developed for the Test cases and are executed Parker Flight Control System Integration Lab (testing environment provided by Parker-Hannifin Corporation).
Real-time data captured from test execution are analyzed for failures and root-cause.
Post-processed scripts are developed to generate reports from data captures.
Failured is analyzed and justified.
Supervised builds of prototype medical lab instruments.
Assisted in writing of assembly procedures.
Experience
2-5 Years
Level
Junior
Education
BA
Verification Engineer Resume
Headline : Responsible for performing routine assignments within standardized procedures and practices with regular supervision to achieve objectives and meet deadlines.
Debugged and repaired failing tests and environment code and scripts, in C++, firmware, Perl, Verilog.
Built/deployed full-chip simulation environment versions and ran regression suites.
Added new memory file splitting/ECC-generation/byte-swapping functionality to simulation launch script.
Identified and modified tests of prior projects to be compatible with new projects.
Created tests and infrastructure for tunneling (GRE and VXLAN).
Worked with DDR3, DDR4, MDDR3, and MDDR4 JEDEC protocols.
Addressed issues during testing.
Experience
5-7 Years
Level
Executive
Education
B.S. In Electrical Engineering
Verification Engineer Resume
Objective : To establish a long-term career in a company where I may utilize my Verification Engineer professional skills and knowledge to be an effective Associate Program Manager and inspiration to those around me.
Skills : Microsoft Office, Labview, C++, C, Assembly language, VHDL, Soldering, Mercurial SCM, SCPI, Sampling Oscilloscope, FreeRTOS, SPI, USB type C, Thunderbolt, PLC, Chinese, Japanese.
Description :
Developed AGE4 tool in C++ and TCL.
Automated regression testing on 88K, PPC, and VSOS Switches.
Reviewed and approved numerous HLDs (High-Level Documents) and DTs (Designers Test plans).
Resolved issues where possible and created Discrepancy Tracking Reports for valid test failures.
Implemented procedural cover group in the master driver.
Debugged issues related to sequences/functional coverage/assertion implementation and resolved bugs.
Designed and simulated macro and standard cells using VCS simulation.
Experience
2-5 Years
Level
Junior
Education
B.Eng. In Electrical Engineering
Verification Engineer Resume
Summary : Verification Engineer with over three years of experience in verifying complex designs of High-Speed Ethernet IP using System Verilog (UVM), Verilog, Perl, and Shell Scripting. Experienced in full verification flow which includes test and coverage plan creation, environment, block functional model and scoreboards creation, test and coverage implementation, and results tracking to delivering fully verified IP designs.
Verified the MAC and Statistics blocks: The MAC implements standard IEEE 802.3 clause 3 features involving frame packaging and processing.
Verified the MACSEC block compliant with IEEE 802.1AE: Created test and coverage plans along with the implementation of tests and functional coverage.
Verified the Receive classifier that would preprocess the frames and extract useful information that would be used by the GCM-AES core.
Designed, verified, performed RTL lint analysis and synthesis of MDIO Master and Slave, compliant with Clause 22 and 45 of IEEE 802.3 Ethernet standard.
Bug analysis tool for mining data from Bugzilla using Perl scripting: This was used in gathering important statistics related to bugs status which helped in methodology improvement.
Verified BPAN compliant with Clause 73 of IEEE 802.3 standard.
Created test and coverage plans along with the implementation of tests and functional coverage for verification of 32G and 16G fiber channel using 64b/66b transmission word format and 8G, 4G, and 2G fiber channel 8b/10b transmission word format.
Experience
7-10 Years
Level
Management
Education
Master of Science
Verification Engineer Resume
Headline : Verification Engineer with 5+ years of experience in Receiving instruction, guidance, and direction from others and uses own knowledge and existing procedures to solve standard problems (EG performing a subset of activities that are related with the different software development phases such as software requirement specification, automation, etc).
Skills : MS Office, Hardware, Computer Skills.
Description :
Played an active role in the verification of the new feature and its release in the SGN project.
Modified UVM Components such as master/slave driver, sequences, and scoreboard for the Sonics fabrics' verification.
Implemented concurrent assertion properties, general sequences and documented them as part of customer release.
Improved functional coverage by evaluating current coverage, writing new cover points, and modifying stimulus.
Added functional cover groups and assertion properties to the RTL using Python scripting.
Responsible for maintenance of random/fixed-configuration regression for all fabric components.
Documented the fabric component's sequences for a feature release.
Experience
5-7 Years
Level
Executive
Education
MS In Electrical Engineering
Verification Engineer Resume
Headline : Responsible for Analyzing, designing, developing, and testing products and servicing, improvements, bug resolutions for integrated hardware and software systems as per customers' requirements.
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